Abstract: To address the low performance and coherence problem in multicore stream processors, this paper proposes a pipeline with stream-based architecture.A hybrid cache system with private first-level cache and shared second-level is also introduced based on the architecture. We analysis the consistency and coherency of the architecture and then verify it on DSP algorithms such as FIR and FFT. According to the result, although the area is increased, the memory access time of the new system decreases by 30%.