黄松, 姜洪雨, 刘智, 耿增建. 一种低噪声高纹波抑制比的LDO设计[J]. 微电子学与计算机, 2018, 35(10): 89-92, 98.
引用本文: 黄松, 姜洪雨, 刘智, 耿增建. 一种低噪声高纹波抑制比的LDO设计[J]. 微电子学与计算机, 2018, 35(10): 89-92, 98.
HUANG Song, JIANG Hong-yu, LIU Zhi, GENG Zeng-jian. Design of a Low Noise High PSR Low Dropout Regulator[J]. Microelectronics & Computer, 2018, 35(10): 89-92, 98.
Citation: HUANG Song, JIANG Hong-yu, LIU Zhi, GENG Zeng-jian. Design of a Low Noise High PSR Low Dropout Regulator[J]. Microelectronics & Computer, 2018, 35(10): 89-92, 98.

一种低噪声高纹波抑制比的LDO设计

Design of a Low Noise High PSR Low Dropout Regulator

  • 摘要: 提出了一种低噪声高电源纹波抑制比(PSR)的低压差线性稳压器(LDO).该低压差线性稳压器通过提高带隙基准和误差放大器的噪声抑制性能以及PSR性能以达到提高LDO性能的目的.在0.6 μm BiCMOS工艺下进行了流片验证, 测试结果表明, 当负载电流为100 mA时, 100 Hz电源纹波抑制比为75 dB; 10 kHz时电源纹波抑制比为72 dB.输出噪声电压(100 Hz~100 KHz)为15 μVRMS.

     

    Abstract: A low dropout regulator (LDO) with low output noise voltage and high power supply ripple rejection ratio (PSR) is described. The LDO improves the ability of power supply ripple rejection and output noise voltage suppression by improving power supply ripple rejection ratio and output noise voltage suppression of the band-gap reference and the differential amplifier. This approach is tested in 0.6 μm BiCMOS process. The results show that the PSR at 100 Hz is 75 dB and at 10 kHz is 72 dB, when the load current is 100 mA. The output noise voltage is 15 μVRMS (100 Hz to 100 kHz).

     

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