Abstract: Considering the shortcomings of the traditional bus system architecture, in order to improve the multi-core system performance, Mesh Network - on - chip (NoC) is designed in this paper.Processor core on the chip links each other through the routers in the NoC, and the communication between nuclears are implemented. The 2D-Mesh topology structure, circuit switching technology and XY routing algorithm can guarantee the delay and throughput of the system, and hardware design language Verilog HDL achieved physical NoC.The FPGA Development Board of Altera company was used to test the NoC, the test result shows that this design on the NoC is correct, and can complete system communication effectively.