基于40 nm CMOS工艺的DAC IP核物理与时序建模

Physical and Timing Modeling of DAC IP Core Based on 40 nm CMOS Process

摘要: 基于40 nm CMOS工艺,分析了DAC模块转化为IP核时所需生成的必要信息,概述了DAC IP核可复用模型的主要特点。对DAC IP核的物理与时序信息进行建模,得到了DAC IP核的物理模型和时序模型,组成了DAC IP核的数据文件交付项。提取得到的IP核模型保护了IP核的设计信息,可满足布局布线、时序分析等基本应用要求.

Abstract: Based on 40 nm CMOS process, the necessary information needed for transforming DAC module into IP core is analyzed, and the main characteristics of reusable models for DAC IP core are outlined. The physical model and timing model of DAC IP core are obtained by modeling the physical and timing information, which are used to form the data file deliveries. The abstracted models can protect the design details, and can meet requirements for basic application, such as place and route, timing analysis.