基于IEEE 1149.7标准的多TAPC芯片的测试和调试技术研究
Test and Debug Technologic Research on Multi-TAPC Chip Based on IEEE 1149.7 Standard
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摘要: 以CJTAG标准和JTAG标准为依据, 在深入研究这两个标准的基础上, 利用Quartus Ⅱ开发平台和Verilog HDL语言设计了多TAPC结构, 并用Modelsim进行仿真验证, 结果表明多TAPC结构能够有效地对多TAPC芯片进行测试和调试.Abstract: In this paper, based on the JTAG Standard and CJTAG Standard, in-depth study on the standards, using the Platform of Quartus Ⅱ and Verilog HDL language to design multi-TAPC architecture and simulation by using the Modelsim simulation tool. The results indicate that multi TAPC architecture can be effictively tested and debugged multi TAPC chip.
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