Abstract: A kind of all-digital clock and data recovery circuit for isolated communication chip is proposed in this paper. The all-digital clock and data recovery circuit is based on the design of a single phase-locked loop structure. It is composed of dual model bang-bang phase and frequency detect, digital machine with binary search and jitter suppressive digital filter, and ladder-shaped ring digital controlled oscillator with three level control word. The circuit is based on standard cell and hardware description language design, with fast locking, low jitter and good portability. Simulation shows that the locking range of this all-digital clock and data recovery is 18~80 MHz, and it finish the frequency locked in 10 μs, the measured peak to peak jitter is about 137.13 ps, RM jitter is 32.39 ps. the circuit consumed the power of 1.279 mW@40 MHz at 1.8 V supply, the layout area is 350 μm×250 μm.