一种采用新型逻辑算法的SAR ADC
An SAR ADC Using A New Type of Logical Algorithm
-
摘要: 基于SMIC 40nm CMOS工艺, 设计了一种12位逐次逼近寄存器式模数转换器(SAR ADC).在正常工作模式的基础上, 增加了当模拟输入信号变化缓慢时, 锁定前4位, 仅转换后8位的工作模式, 降低了ADC的功耗, 提高了ADC的采样率, 同时分辨率保持不变.当模拟输入信号变化较大时, ADC又可重新回到正常工作模式.在1.1 V的电源电压, 3.6 MS/s的采样率下, ADC总功耗为43 μW, 品质因数FOM为10.1fJ/(conv.·step).Abstract: A 12-bit successive-approximation-register analog-to-digital converter (SAR ADC) was designed in SMIC 40nm CMOS process. Base on traditional SAR logic, add an algorithm of when analog input signal changes slowly, ADC locking its first 4 bits, and only do last 8 conversions. And when analog input signal has great change, ADC returns to normal working mode. It decreases power consumption and increase sampling rate of ADC, but doesn't change resolution of ADC. Under a 1.1V supply and 3.6 MS/s sampling rate, the total power consumption of ADC is 43 μW, and the FOM is 10.1fJ/(conv.·step).