Abstract: A high-performance VLSI implementation of JPEG-LS algorithm for lossless/near-lossless image compression was proposed in this paper.After analyzing the bottlenecks in JPEG-LS, a semaphore collection mechanism was employed to avoid pipeline interruption in the part of context buffer.The fully-pipelined structure ensured its feasibility to high-speed image processing system, in which ultra-high-throughput is required.Benefiting from its highly-parameterized design, host systems could dynamically adjust and optimize algorithm parameters, in order to adapt compression result and efficiency to different environments.The implementation was verified on FPGA platform, and the result shows high performance that was close to or exceeding other ASIC implementation.