苏鹏洲, 黄鲁, 张步青. 一种用于串行Rapid IO接口的差分接收机设计[J]. 微电子学与计算机, 2015, 32(10): 185-188. DOI: 10.19304/j.cnki.issn1000-7180.2015.10.040
引用本文: 苏鹏洲, 黄鲁, 张步青. 一种用于串行Rapid IO接口的差分接收机设计[J]. 微电子学与计算机, 2015, 32(10): 185-188. DOI: 10.19304/j.cnki.issn1000-7180.2015.10.040
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SU Peng-zhou, HUANG Lu, ZHANG Bu-qing. Design of a Differential Receiver Used in Serial Rapid IO Interface[J]. Microelectronics & Computer, 2015, 32(10): 185-188. DOI: 10.19304/j.cnki.issn1000-7180.2015.10.040
Citation: SU Peng-zhou, HUANG Lu, ZHANG Bu-qing. Design of a Differential Receiver Used in Serial Rapid IO Interface[J]. Microelectronics & Computer, 2015, 32(10): 185-188. DOI: 10.19304/j.cnki.issn1000-7180.2015.10.040
shu

一种用于串行Rapid IO接口的差分接收机设计

Design of a Differential Receiver Used in Serial Rapid IO Interface

    摘要
  • 摘要: 基于串行Rapid IO 2.0规范,设计了一种用于串行Rapid IO接口的差分接收机.该接收机均衡电路的频率补偿点以及补偿强度可调,以满足Rapid IO 2.0规范规定的不同传输数据率的传输要求;采用共模稳定与偏移调整电路,以减小工艺和温度对接收机的影响.基于SMIC 40 nm CMOS工艺对电路进行设计.仿真结果显示,该差分接收机满足Rapid IO 2.0规范,在6.25 Gb/s的最大数据率下,平均功耗为1.3 mW.

     

    Abstract: A differential receiver used in Serial Rapid IO Interface was designed, which is based on Rapid IO 2.0 specification. The compensation frequency and strength of receiver can be adjustable to meet the requirements of different transmission data rates which are stipulated in Rapid IO 2.0 specification, and common-voltage stabling and offset adjusting circuit was also designed to reduce the influence of process and temperature on the receiver. The differential receiver was designed in SMIC 40 nm CMOS process. Simulation results showed that the differential receiver meets Rapid IO 2.0 specification, the average power consumption is 1.3 mW at 6.25 Gb/s maximum data rate.

     

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