Abstract: Analyses the characteristics and shortcomings of single-layer AHB bus, and proposes and implements an architecture of AHB bus matrix which is configurable, hierarchical and efficient according to the requirement of the design base on MIPS14K core. This bus matrix in accordance with the protocol standard of AHB Lite and support parallel access of multiple MASRER/SLAVE. This architecture could improve effectively the system bandwith, reduce the bus arbitration delay and improve the overall performance of embedded SoC chip. This AHB bus matrix has been applied to an lightweight embedded SoC chip, completed FPGA prototype verification and achieve the layout design.