Abstract: This paper researches and implements a reconfigurable arithmetic logic unit (RALU) on 64bit digital signal processor, which is made up of processing elements(PE) based on 4×4 2-Dimension array through changing the form of switch interconnection. It could execute 32 and 64bit fixed-point operations of basic and reconfigurable type, 32, 40 and 64 bit floating-point operations of basic and reconfigurable type. To reduce circuit resources and design complexity, RALU adopts primary technologies, including reusable 64 bit fixed-point multiplier, right and left shift shifter, uniform fixed/floating-point models of decoding and computing. When RALU is synthesized and implemented by FPGA with xc6vsx315t-1ff1759, its resource is 15347 LUTs and frequency is above 100 MHz.