梁帅, 卫宝跃, 刘昱, 张海英. 24位低功耗音频Sigma-Delta数模转换器数字前端实现[J]. 微电子学与计算机, 2015, 32(5): 36-40. DOI: 10.19304/j.cnki.issn1000-7180.2015.05.008
引用本文: 梁帅, 卫宝跃, 刘昱, 张海英. 24位低功耗音频Sigma-Delta数模转换器数字前端实现[J]. 微电子学与计算机, 2015, 32(5): 36-40. DOI: 10.19304/j.cnki.issn1000-7180.2015.05.008
LIANG Shuai, WEI Bao-yue, LIU Yu, ZHANG Hai-ying. Efficient Implementation for Digital Part of 24 Bit Audio Sigma-Delta DAC with Low Power[J]. Microelectronics & Computer, 2015, 32(5): 36-40. DOI: 10.19304/j.cnki.issn1000-7180.2015.05.008
Citation: LIANG Shuai, WEI Bao-yue, LIU Yu, ZHANG Hai-ying. Efficient Implementation for Digital Part of 24 Bit Audio Sigma-Delta DAC with Low Power[J]. Microelectronics & Computer, 2015, 32(5): 36-40. DOI: 10.19304/j.cnki.issn1000-7180.2015.05.008

24位低功耗音频Sigma-Delta数模转换器数字前端实现

Efficient Implementation for Digital Part of 24 Bit Audio Sigma-Delta DAC with Low Power

  • 摘要: 为实现24 bit音频DAC的数字前端低功耗、微面积的设计,提出了一种新的面积优化方法.优化了有限冲击响应(FIR)插值滤波器结构,同时采用改进的非递归公共子式消除算法和加法器、寄存器共用的方法来减小硬件开销和面积.优化的4阶3 bit Sigma-Delta调制器克服了单比特量化器需随机加抖的问题和减轻了对后续模拟重建滤波器的性能要求.该数字部分采SMIC 40 nm 1P6M标准CMOS工艺设计,核心芯片面积为0.058 mm2,在1.1 V电源电压仿真下,得到功耗为53 μW,峰值信噪比(SNR)达到了146 dB,谐波失真(THD)为-150 dB,实现了高性能低功耗的要求.

     

    Abstract: One area-efficient technique is applied to accomplish digital front-end of 24-bit audio digital-to-analog converter (DAC) with low power consumption and less area. For reducing hardware overhead and area, finite-impulse response (FIR) filter is implemented with optimized structure, improved non-recursive common sub-expression elimination, adders and registers reusability. Optimal 4th order 3 bit sigma delta modulator overcomes the need of dither and relaxes the requirement of analog post filtering. The digital part is implemented in SMIC 40nm 1P6M process, the total core area is 0.058 mm2. From the simulation of this digital part with the power supply of 1.1 V, the power consumption is 53 μW. At the same time, the peak signal to noise (SNR) achieves 146 dB, and THD is -150 dB.

     

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