Abstract: In order to realize flexible integration and efficient communication of Chiplet systems, a Dual Independent Ring interconnection architecture (DIR) for different Chiplet systems integration was proposed. By means of splicing two independent arc-shaped networks and co-control modules, a deadlock free annular interconnecting channel is formed. The side routing node allocation mechanism with self-checking function is used to flexibly and evenly allocate the built-in side routing nodes of different Chiplet systems, avoiding the repeated design and verification of switching board. Hardware description language is used to implement the interconnection architecture, and the side routing node allocation mechanism and interconnection architecture are tested. Simulation and experimental results show that the routing node allocation mechanism can evenly allocate any number of side routing nodes in a short time. At the same injection rate, DIR has lower average latency compared with grid interconnection and Dataline-Buffer-Node(DBN) interconnection. Compared with the grid interconnection architecture, DIR reduces power consumption by nearly 16% and resource usage by nearly 7 times.