一种基于22 nm FDSOI工艺的低噪声快速锁定电荷泵锁相环

侯灵岩; 刘云涛; 方硕; 王云

doi:10.19304/J.ISSN1000-7180.2022.0768

一种基于22 nm FDSOI工艺的低噪声快速锁定电荷泵锁相环

A low noise fast locking charge pump phase locked loop based on 22 nm FDSOI process

摘要

摘要: 基于22 nm 全耗尽绝缘体上硅（Fully Depleted Silicon-On-Insulator, FDSOI）工艺设计了一种能够快速锁定的电荷泵锁相环（Charge Pump Phase Locked Loop, CPPLL）电路，该锁相环利用FDSOI器件背栅偏置的特点来提升压控振荡器性能，采用了无死区的鉴频鉴相器（Phase Frequency Detector, PFD）和低失配电流电荷泵（Charge Pump, CP）以及低相位噪声结构的压控振荡器（Voltage Controlled Oscillator, VCO）。研究了相位噪声的理论模型，基于理论参数进行电路设计和电路噪声降低。仿真结果表明，该锁相环锁定时间3 μs，CP电流失配小于1%，VCO相噪水平达到−100.4 dBc/Hz@1 MHz，版图面积为0.14 mm²。该锁相环具有锁定速度快，相噪低，频率精准等优点。

Abstract: A Charge Pump Phase-Locked Loop (CPPLL) circuit is designed based on the 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) process. The circuit makes full use of the back gate bias of FDSOI device to improve the performance of Voltage Controlled Oscillator (VCO). It is composed of a Phase Frequency Detector (PFD), a Charge Pump (CP) and a VCO with low phase noise. The system simulation and phase noise are carried out from the theoretical model, and then the circuit design and circuit noise reduction are carried out based on the theoretical parameters. The simulation results show that the Phase Locked Loop (PLL) has a locking time of 3 μs, the charge pump mismatch current is less than 1%, the phase noise of VCO reaches −100.4 dBc/Hz@1 MHz, and the layout area is 0.14 mm². It shows that the circuit has the advantages of fast locking, low phase noise and accurate output frequency.

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