Abstract: In recent years,private L2 Cache is the mainstream architecture for high-performance multi-core processors,but it requires multiple memory accesses to maintain Cache consistency, which increases system overhead.Therefore,this paper proposes a multi-core Cache coherency design based on on PowerPC instruction architecture, which integrates private Cache state machine and on-chip bus monitoring mechanism, so that processors can directly exchange data through intervention interface.The multi-core Cache structure is designed and implemented by Verilog HDL,a hardware description language,and the simulation results show that when implementing Cache consistency,compared with the traditional memory access method,this structure with intervention path can save 87.06% time,and the performance of multi-core processor is effectively improved.Finally, the test results of real chip on board level are consistent with the simulation results.