Abstract: In the design of large-scale digital integrated circuit, timing analysis is a key part of signoff. At present, the method of optimizing circuit timing in circuit design is critical path optimization, but this kind of method may change the circuit structure, make a lot of changes to the circuit layout, and prolong the chip design cycle. In order to quickly solve the problem of circuit timing correction, a time shift flip-flop (TSDFF) based on dynamic circuit design idea is proposed. The TSDFF removes setup time, simulation and the layout design based on SMIC40nm process. By properly allocating parameters, timing parameters are superior to DFFs in the standard cell library, PVT (Process,Voltage,Temperature) simulation shows that in typical cases, the TSDFF clock output delay speedup ratio reaches 188.9% compared to the DFF with the same drive capability in the standard cell library. Combined with the TSDFF and Timing Borrow method, the path timing allocation in digital chips is analyzed. The TSDFF can be applied to the timing fix and optimization of digital circuits in the stage of Engineering Change Order (ECO), which can reduce clock tree and logic circuit adjustment, and effectively shorten the design cycle of digital circuit chips.