Abstract: True random number generator (TRNG) and physical unclonable functions (PUF) are important basic security primitives of security encryption authentication system. However, traditional TRNG usually has additional post-processing circuits. For circuits that realize TRNG and PUF structures simultaneously through two different modules, the area consumption is too large and the structure is complex. Therefore, based on the optimization of TRNG, this paper uses FPGA to implement a lightweight integrated design of TRNG and PUF for IOT devices. TRNG is implemented by using fast carry chain logic and traditional RO-PUF is improved by using fixed comparison chain and multiple detection. The proposed structure was validated by using the PYNQ-Z2. Experimental results show that the TRNG structure passes the test of NIST SP 800-22 without post-processing process, and achieves a throughput of 125 Mbps with 0.999997 bits of Shannon entropy. The improved PUF has good uniformity, stability and desired uniqueness, which are 47.45%, 99.48% and 50.12% respectively.