Abstract: The grid-based routing method is the main means of printed circuit boards (PCB) routing. As the component density and functional complexity of circuit systems continue to increase, the challenges of PCB routing rapidly grow. While routing map size and component obstacles increase, the commonly used PCB routing algorithms such as Lees and A* have a dramatically increasing search space and cannot effectively solve the problem of multiple network routing sequences. To address these problems, a routing acceleration strategy based on the idea of segmented parallelism is proposed to improve the routing efficiency. The basic idea is to decompose the search problem in an original large area into parallel search problems within multiple smaller areas, and adopt an adaptive heuristic guidance function to adapt to the feature of multiple areas. In this way, the huge search space can be effectively reduced, thus accelerating the routing process. The simulation experiments show that in a 150×150 grid map, the proposed method can improve the search speed by 160 times and 17 times compared with the Lees and A* algorithms, respectively.