Abstract: Clock phase modulation circuits are widely used in high data-rate Serializer-Deserializer (Serdes) technology and clock data recovery circuits. To implement the low-complexity and high accuracy multi-phase clock, is a key part for improving Serdes’s performances. In this paper, an improved digital-to-analog conversion structure combining coarse and fine adjustment is proposed, which improves the accuracy of multi-phase interpolation of the clocks. It is a 64-phase high-speed clock signal phase modulation circuit. In this circuit, the dual differential constant current amplifiers with multiple independent current sources and the dual differential constant current amplifiers with shared current sources are used to realize the combination of coarse adjustment and fine adjustment. This digital phase modulated clock has the advantages of low complexity, high frequency, strong stability and high precision. The high-speed clock phase modulation circuit was implemented based on SMIC 55 nm CMOS technology, the layout area is 0.039 mm². The theoretical analysis of the circuit shows that, with the phase interpolator structure, the maximum deviation of DNL and INL is about 1°.