秦爽, 李健, 陈杰. 面向GNSS信道译码的RISC-V专用指令设计[J]. 微电子学与计算机, 2021, 38(11): 61-66. DOI: 10.19304/J.ISSN1000-7180.2021.0061
引用本文: 秦爽, 李健, 陈杰. 面向GNSS信道译码的RISC-V专用指令设计[J]. 微电子学与计算机, 2021, 38(11): 61-66. DOI: 10.19304/J.ISSN1000-7180.2021.0061
QIN Shuang, LI Jian, CHEN Jie. Design of RISC-V dedicated instructions for GNSS channel decoding[J]. Microelectronics & Computer, 2021, 38(11): 61-66. DOI: 10.19304/J.ISSN1000-7180.2021.0061
Citation: QIN Shuang, LI Jian, CHEN Jie. Design of RISC-V dedicated instructions for GNSS channel decoding[J]. Microelectronics & Computer, 2021, 38(11): 61-66. DOI: 10.19304/J.ISSN1000-7180.2021.0061

面向GNSS信道译码的RISC-V专用指令设计

Design of RISC-V dedicated instructions for GNSS channel decoding

  • 摘要: 随着全球卫星导航系统(GNSS)信号的增多,导航接收机需要处理的信道译码算法越来越多.传统的使用协处理器的方式虽然可以提高信道译码的速度,但是会消耗大量硬件资源.采用软件实现信道译码的方式虽然可以使用DSP、SIMD等指令集进行加速,但是这些指令集不是仅针对信道译码进行扩展的,其中大部分指令在信道译码中很少使用,因此导致信道译码效率较低.基于RISC-V指令集针对GNSS信道译码扩展7条专用指令,这些专用指令丰富了RISC-V的位操作.对比相同的信道译码程序,优化后的算法代码量降低,其中BCH译码和解交织算法代码量减少50%.gem5模拟器和自设计RISC-V处理器Nightcore验证结果表明,优化后的算法运行周期数降低,其中解交织算法降低92%.

     

    Abstract: With the increase of global navigation satellite system(GNSS) signals, more and more channel decoding algorithms need to be processed by navigation receivers. Although the traditional method using a coprocessor can improve the efficiency of channel decoding, it consumes a lot of hardware resources. Using software to implement channel decoding can use instruction sets such as DSP and SIMD for acceleration, but these instruction sets are not only extended for channel decoding, and most of the instructions are rarely used in channel decoding algorithms. In this way, the channel decoding efficiency is low. Based on the RISC-V instruction set, seven dedicated instructions are extended for GNSS channel decoding. These dedicated instructions enrich the bit manipulations of RISC-V. Compared with the same channel decoding program, the optimized algorithm code amount is reduced. The BCH and deinterleave algorithm code amount reduced by 50%. The gem5 simulator and self-designed RISC-V processor Nightcore verification results show that the number of cycles of the optimized algorithm is reduced. Among them, the number of operating cycles of the deinterleave algorithm is reduced by 92%.

     

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