Abstract: This paper studies the design and optimization method of low-power clock tree under nanotechnology. Based on the two design variables, the transition time and the load capacitance of the clock signal, and the parasitic resistance-capacitance model of the clock networks, the paper shows that, with the reduced width or enlarged space of the metal wire, the power consumption of the clock tree can be reduced, meanwhile, the timing of the clock tree can also be violated.. Therefore, this paper proposes one joint optimization method of clock tree with low-power and low timing violations, and gives a low power clock tree synthesis design flow. The results show that, compared with the general rules of experience method, the optimization method proposed in this paper can reduce the dynamic power consumption of the clock network by 10.3%and reduce the total timing violation by 7.07% under typical condition.