Abstract: In the process of chip design, timing model extraction is one of the key of static timing analysis. Different complex D flip-flop and domino structure need different approaches based on the NanoTime to solve complex topology recognition error, which improves the effectiveness of timing model. The simulation results are shown using an actual case. The simulation data shows that effective timing model can be achieved according to the method provided by this paper. At the present, the corresponding design flow has been invested and successfully applied in practical engineering implementation. This also means it has practical applications value of reliability and it is necessary for engineering implementation.