Abstract: Dual Interlocked Storage Cell (DICE) is a reliable and effective method for Single Event Upset (SEU) reinforcement in maintaining state. However, SEU still occur in DICE cell-based SRAM, due to the weakness 0f DICE cell during reading and writing. Compared with the single node, the effect of DICE resistance multiple-node upset is weak. A separated-read-write structure is proposed to handle the DICE cell's upset during reading and writing. And according to the resistance reinforcement principle, Transistor DICE (TDICE) is used that adding NMOS between the events of DICE. TDICE increases the effect of DICE resistance multiple-node upset through the connection between events in a transistor isolation feedback loop. The simulation results show that, TDICE shows a nearly complete tolerance SET with multiple-node upset. Spectre simulation results show that the SRAM based on the TDICE unit has a strong ability to resist a single event upset.