Abstract: AViterbi decoder is designed and implemented for (2,1,7) convolutional code in the SBAS and Galileo navigation systems. Since the data rate of the satellite navigation system is relatively low, the sequential architecture is applied and the Viterbi decoder is reused by all data channels in order to reduce area consumption. In addition, modified add-select-compare unit and register-exchange method have been used to further optimize the circuit. In order to reduce storage usage, RAM is accessed by in-place updating technology for path metric and survivor path. The decoder has been verified on the FPGA platform, and the synthesis result shows that the area of the logic circuit is 4 738 μm² using 65 nm cell library.