Abstract: Design of the 1.5bit sub-ADC applied to 14 bit low-power pipeline ADC circuit.The circuit is fabricated in a 0.18μm standard CMOS process provided by SMIC.The sub-ADC mainly includes the core module comparator circuit and the encoder circuit.The high speed is realized by using the dynamic latch comparator which is composed of the preamplifier and the latch.In order to reduce the power consumption of pipelined ADC, a new structure of sub-ADC circuit is proposed, which can realize the sharing of the preamplifier in the adjacent comparator.Increase the reset switch circuit to reduce Kickback noise and eliminate the mutual interference between the two latches.The simulation results show that the input and output correct flip in 100 MHz sampling frequency at 3Vsupply voltage.The transmission delay is 1.73 ns, and the power consumption is 157.28 uA.Can meet the high accuracy and low power pipeline ADC performance requirements.