胡孔阳, 韩琼磊, 顾大晔. 一种SRIO交换器内部网络设计[J]. 微电子学与计算机, 2018, 35(9): 10-13.
引用本文: 胡孔阳, 韩琼磊, 顾大晔. 一种SRIO交换器内部网络设计[J]. 微电子学与计算机, 2018, 35(9): 10-13.
HU Kong-yang, HAN Qiong-lei, GU Da-ye. ASRIO Switch Inside Network Design[J]. Microelectronics & Computer, 2018, 35(9): 10-13.
Citation: HU Kong-yang, HAN Qiong-lei, GU Da-ye. ASRIO Switch Inside Network Design[J]. Microelectronics & Computer, 2018, 35(9): 10-13.

一种SRIO交换器内部网络设计

ASRIO Switch Inside Network Design

  • 摘要: 针对SRIO交换器数据通路的特点, 提出了一种交换器内部的互连网络设计.重点解决了实现交换网络的三个问题:1.SRIO端点与端点的跨时钟域转换; 2.SRIO传输层包的组合与拆分; 3.多个源端点向同一个目的端点请求时的仲裁.使用VerdilogHDL对设计进行了描述, 同时设计了SRIO端点模型并与之互连, 对交叉网络进行随机测试, 通过自动化比对收、发端点的数据包验证设计的正确性.经过验证, 本设计可以利用SRIO端点控制器IP基于ASIC或FPGA构建SRIO交换器.

     

    Abstract: According to the characteristics of SRIO switch data path, we proposed one design to build switch inside network. Focus on solving three problems to make switch network:1.Clock domain crossing between SRIO endpoint to endpoint; 2.SRIO transmission line's package merging and splitting; 3. Arbitration between multi-source endpoint to the same endpoint. We used VerdilogHDL to describe this design, and also design the SRIO endpoint model to connect with the network, to make the random test, we check the input and output package to verify the correctness automatic. The verification proves that this design can use SRIO end point controller in ASIC or FPGA to build SRIO switch.

     

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