Abstract: In this paper, we implement RSA cryptographic using Residue number system (RNS). We choose four modulo similar in the form for every computational unit. The reduction unit supports these four modulo is smaller and shorter than the required reduction unit corresponding to the conventional method selection. According to our proposed method, we select seven groups of modulo with a width of 74, and design a RNS Montgomery multiplier based on Cox-Rower architecture to implement RSA cryptography. In the SMIC 0.13 μm standard cell library, clock frequency reaches up to 278 MHz. At this frequency, 1 024, 2 048-bit RSA decryption in Chinese Remainder Theorem (CRT) mode and 1 024-bit RSA decryption require 710 μs, 99 μs, 350 μs, respectively, faster than the published related designs.