Abstract: To solve the problem of poor universality of the on-board solid-state storage system, a general on-board solid-state storage controller is designed by using the standard on-chip bus (APB bus) architecture and the method of introducing the parameter configuration layer. The design can support different FLASH chip manufacturers, different FLASH chip capacities, and NAND FLASH memory arrays with different stacked configurations, so that a set of codes can be adapted to various engineering tasks, which can effectively reduce development costs, shorten the development process and improve development efficiency. The design supports FLASH read/write, erase, reset and other functions, and has a bad block management mechanism, which can effectively enhance the stability of the system and improve storage efficiency. The experimental results show that the design has a maximum write rate of 100 Mbps and a maximum capacity of 256 Gbit, which can adapt to different FLASH chip configurations and compatible with mainstream aerospace FLASH chips.