王晋, 田泽, 唐龙飞. 采用ADC的100BaseTX以太网收发器设计[J]. 微电子学与计算机, 2016, 33(8): 126-129.
引用本文: 王晋, 田泽, 唐龙飞. 采用ADC的100BaseTX以太网收发器设计[J]. 微电子学与计算机, 2016, 33(8): 126-129.
WANG Jin, TIAN Ze, TANG Long-fei. Design of a Transceriver With ADC for 100BaseTX Ethernet[J]. Microelectronics & Computer, 2016, 33(8): 126-129.
Citation: WANG Jin, TIAN Ze, TANG Long-fei. Design of a Transceriver With ADC for 100BaseTX Ethernet[J]. Microelectronics & Computer, 2016, 33(8): 126-129.

采用ADC的100BaseTX以太网收发器设计

Design of a Transceriver With ADC for 100BaseTX Ethernet

  • 摘要: 设计了一款面向100BaseTX以太网的收发器芯片.该收发器接收端采用模拟线性均衡和判决式反馈均衡(DFE)的混合结构, 并采用模数转化器在数字域实现自适应均衡和基线漂移补偿.为了降低功耗和减小芯片面积, 提出了一种连续时间线性均衡气和可变增益放大器共享电阻、电容的电路结构.该收发器采用0.13 μm 1.2 V CMOS工艺实现, 线缆传输距离大于100 m.

     

    Abstract: This paper describes a 100BaseTX Ethernet physical layer interface with ADC in 1.2 V 0.13 μm CMOS technology. A continuous-time linear equalizer (CTLE) and a decision-feedback equalizer (DFE) are used in receiver. The circuit uses digital techniques to perform adaptive line equalization and baseline wander compensation through analog-to-digital convertor. The proposed CTLE and variable-gain amplifier (VGA) mixed structure shareing resistor and capacitance, can decrease low power and small area. The transceiver allows for robust performance for cable lengths>100 m.

     

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