刘滢浩, 刘宏, 徐乐, 田彤. 一种Vcm-Based10位16M采样率低功耗逐次逼近型模数转换器[J]. 微电子学与计算机, 2017, 34(11): 99-103.
引用本文: 刘滢浩, 刘宏, 徐乐, 田彤. 一种Vcm-Based10位16M采样率低功耗逐次逼近型模数转换器[J]. 微电子学与计算机, 2017, 34(11): 99-103.
LIU Ying-hao, LIU Hong, XU Le, TIAN Tong. A 10-bit 2 Ms/S SAR ADC with Vcm-Based Switching Scheme[J]. Microelectronics & Computer, 2017, 34(11): 99-103.
Citation: LIU Ying-hao, LIU Hong, XU Le, TIAN Tong. A 10-bit 2 Ms/S SAR ADC with Vcm-Based Switching Scheme[J]. Microelectronics & Computer, 2017, 34(11): 99-103.

一种Vcm-Based10位16M采样率低功耗逐次逼近型模数转换器

A 10-bit 2 Ms/S SAR ADC with Vcm-Based Switching Scheme

  • 摘要: 针对无线传感网络中低功耗无线传感器的应用, 设计了一种采样速率为16 MSPS, 精度10 bit的全差分超低功耗逐次逼近型模数转换器(SAR ADC).提出一种基于Vcm-Based参考电压的开关切换逻辑, 减少DAC模块参考电压开关切换的功耗.同时, DAC电容阵列模块采用分段式结构, 单位电容采用优化的MOM电容, 有效提高ADC的匹配性和精度; 此外采用了双尾电流型动态锁存比较器, 实现功耗的最优化.芯片采用CMOS 65 nm工艺设计, 后仿结果显示在1.2 V电源电压及16 MSPS采样率下, ADC有效位数达到9.42 bit, 功耗为140 μW, 品质因数(FOM)为12.8 fJ/Conversion-step.

     

    Abstract: Aiming at the application of low power wireless sensor in wireless sensor network, a ultra low power Successive Approximation Register Analog-to-Digital Converter (SAR ADC) has been designed. A switching logic based on Vcm-Based reference voltage is proposed to reduce the power consumption of the DAC when the reference voltage is switched. The DAC capacitor array module uses the sectional structure, the unit capacitance uses the optimized MOM capacitance, enhances the ADC matching and the precision effectively. In addition, a double tail current dynamic latch comparator is used to optimize the power consumption. The ADC is implemented in CMOS 65 nm technology. The post simulation results shown that under 1.2 V supply voltage, the sampling rate is 16 MSPS, the power consumption is 140 μW, effective number of bits reached 9.42 bit, and the figure-of-merit (FOM) is 12.8 fJ/conversion-step.

     

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