基于45 nm SOI CMOS工艺的10 bit、125 MS/s过零检测Pipeline-SAR ADC设计
A 10 bit 125 MS/s Zero Crossing Detection Pipeline-SAR ADC Based on 45 nm SOI CMOS Technology
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摘要: 基于45 nm SOI CMOS工艺, 设计了一款两级流水线级联型逐次逼近ADC(Pipeline-SAR ADC).摒弃了传统流水线结构中大功耗级间运算放大器, 采用过零比较器和受控电流源完成级间余量放大功能, 极大地减小了ADC的功耗.分析了子ADC中比较器失调对ADC精度的影响, 提出了一种具有失调校准的动态比较器, 满足了高精度、高速度的要求.此外, 在设计逐次逼近结构时, 采用共模切换、上极板采样和全定制控制逻辑等技术进一步降低了系统功耗.仿真结果显示, ADC在125 MS/s、奈圭斯特输入频率下, 实现了60.46 dB的信噪失真比和77.33 dB的无杂散动态范围, 有效位数为9.75 bit, 系统总功耗只有1 mW.ADC的FoM值仅为9.29 fJ/step, 较其他工作有很大的提升.Abstract: A two-stage pipeline-SAR ADC is designed in this paper based on 45nm SOI CMOS technology. A zero crossing comparator and controlled current source are used to replace the power-hungry OTA to achieve residual amplification, which reduces the power consumption of ADC greatly. The impact of comparator offset on ADC resolution is analyzed, and a dynamic comparator with calibration is proposed to meet the requirement of high resolution and high speed. Besides, in the design of successive approximation structure, the power is further reduced by adopting common-mode switching, top-plate sampling and full custom control logic. Simulation results show that the signal to noise distortion ratio, spurious free dynamic range and effective number of designed ADC are 60.46 dB, 77.33 dB and 9.75 bit, respectively, at 125 MS/s with Nyquist input frequency. The ADC consumes only 1mW and obtains a much smaller figure-of-merit of 9.29fJ/step comparing with other state of arts.
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