尹勇生, 邓春菲, 陈红梅. 高精度Sigma-Delta调制器的建模设计[J]. 微电子学与计算机, 2016, 33(5): 28-32.
引用本文: 尹勇生, 邓春菲, 陈红梅. 高精度Sigma-Delta调制器的建模设计[J]. 微电子学与计算机, 2016, 33(5): 28-32.
YIN Yong-sheng, DENG Chun-fei, CHEN Hong-mei. The Modeling Design of High-precision Sigma-Delta Modulator[J]. Microelectronics & Computer, 2016, 33(5): 28-32.
Citation: YIN Yong-sheng, DENG Chun-fei, CHEN Hong-mei. The Modeling Design of High-precision Sigma-Delta Modulator[J]. Microelectronics & Computer, 2016, 33(5): 28-32.

高精度Sigma-Delta调制器的建模设计

The Modeling Design of High-precision Sigma-Delta Modulator

  • 摘要: 基于MATLAB Simulink设计实现了一款单环三阶一位量化CIFF (Cascade-of-integrators, feedforward form)结构的高精度Sigma-Delta调制器.通过对噪声传输函数和系统反馈系数进行优化, 提高了调制器的稳定性; 分析了开关电容电路的主要误差影响, 为电路实现提供可靠的设计指导.仿真结果显示, 在输入信号带宽为75 Hz, 过采样率为512时, 理想调制器输出SNR高达148.3 dB, ENOB为24.34 bit; 考虑非理想因素时, ENOB为22.02 bit; 电路级实现的调制器ENOB达20.94 bit, 表明该设计可实现低信号带宽下高精度转换.

     

    Abstract: Based on the MATLAB Simulink, the design of high-precision Sigma-Delta Modulator with single-loop third-order one-bit structure of CIFF is realized. The noise transfer function and feedback coefficients are optimized to enhance the stability of the system; and the main non-ideal factors in switch capacitor circuit are analyzed to provide a reliable guidance for transistor level circuit design. The simulation results show that when the signal bandwidth is 75 Hz and the sampling rate is 512, the SNR is as high as 148.3 dB; the ENOB is 24.34 bit and become 22.02 bit in the condition of various non-ideal factors, and become 20.94 bit when the designed modulator is realized by the real circuit. The results show that this structure can achieve high accuracy under low signal bandwidth.

     

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