Abstract:
As an important new generation of bus technology, the Fibre Channel protocol has the excellent features of high bandwidth, strong scalability, high reliability, real-time performance, supporting for multiple media, and immunity to electromagnetic interference. It has developed rapidly and has been widely used in many fields. This article carries on the thorough research to the PCS layer of the FC protocol, and analyzes its key modules: elastic buffer, 8B/10B codec, bit-width converter, synchronizer, etc. And it proposes an overall design architecture, uses verilog language to complete code design, builds a loopback verification platform, and uses the FC protocol analyzer, combined with FPGA verification to complete the design.