Abstract: In order to fathom the effect on three-dimensional FPGA performance after IP cores are integrated, two FPGA structures are introduced in this paper: homogeneous 3D FPGAs with IP cores and coarse-grained heterogeneous ones.In the first place, we developed a new FPGA CAD tool, which is an upgrade version of a 2D FPGA CAD tool, to support FPGAs based on IP cores and 3D switch boxes, then use it to analyze the homogeneous 3D FPGA performance in different layers in terms of quality and quantity. Experiments reveal the fact that with the number of chip layer increases, total chip area will rise, in the other hand, critical path delay and chip area per layer fall accordingly. Compared to the homogeneous 3D structured FPGAs (with IP cores), coarse-grained heterogeneous ones have better critical path delay, which proves such structure has the effectiveness on reducing critical path delay.