李卯良, 李涛, 刘欢, 杨铮, 郭佳乐, 李明, 宋晨阳. 时钟共享多线程处理器存储结构的设计与实现[J]. 微电子学与计算机, 2017, 34(1): 110-113,118.
引用本文: 李卯良, 李涛, 刘欢, 杨铮, 郭佳乐, 李明, 宋晨阳. 时钟共享多线程处理器存储结构的设计与实现[J]. 微电子学与计算机, 2017, 34(1): 110-113,118.
LI Mao-liang, LI Tao, LIU Huan, YANG Zheng, GUO Jia-le, LI Ming, SONG Chen-yang. Design and Implementation of Clock Shared a Multithreaded Processor Storage Structure[J]. Microelectronics & Computer, 2017, 34(1): 110-113,118.
Citation: LI Mao-liang, LI Tao, LIU Huan, YANG Zheng, GUO Jia-le, LI Ming, SONG Chen-yang. Design and Implementation of Clock Shared a Multithreaded Processor Storage Structure[J]. Microelectronics & Computer, 2017, 34(1): 110-113,118.

时钟共享多线程处理器存储结构的设计与实现

Design and Implementation of Clock Shared a Multithreaded Processor Storage Structure

  • 摘要: 针对时钟共享多线程处理器(SMT_PAAG)中指令和数据存取速率的需求, 提出了一种时钟共享多线程处理器交叉存储结构.该结构分为数据交叉存储和指令交叉存储, 其中数据交叉存储实现了前向处理单元和多线程处理单元(Processing Element, PE)的数据交互、线程间数据交互以及线程内部数据存取; 指令交叉存储实现了PE内部线程的指令存取.在FPGA上实现结果表明, 该交叉存储结构能够满足多线程处理器对于指令和数据存取速率的需求, 最高工作频率可达518.309 MHz.

     

    Abstract: For clock shared a multithreaded processor(SMT_PAAG)of instructions and data transfer rate indemand, proposes a shared clock multithreaded processor cross storage structure.The structure is composed of data storage and instruction cross storage.The data storage exchange between the front processing unit and the multi thread processing unit(Element Processing, PE)is realized, data interactions between threads, and thread the internal data access.Instruction cross storage to achieve the PE internal thread instruction access.Implemented on the FPGA results show that the cross-storage structures can meet a multithreaded processor for instructions and data transfer rate of the demand, the highest frequency can reach 518.309 MHz.

     

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