基于TSV Array的三维集成电路优化设计研究
TSV Array-Based 3D ICs Design Exploration and Optimization
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摘要: 通过在三维集成电路中使用TSV阵列, 分析TSV阵列对于提高可靠性的同时给时序和布局布线等带来的负面影响.基于TSV阵列, 完成三维集成电路后端流程设计和HEVC运动估计电路的三维实现.实验表明基于3×3 TSV阵列的三维集成电路, 每个TSV阵列可以实现1个TSV的冗余, 可靠性提高11.98%, 功耗和布线上分别增加了19.6%和19.2%.Abstract: This paper analysis TSV array's positive effect on circuit's reliability and negative effect on timing and wire length by complete the 3D circuit (HEVC motion estimation circuit) back-end design with it. Results of the research indicated that one TSV array could have one redundant TSV in a 3*3 TSV array, and the reliability improved 11.98%, power consumption and wire length increased 19.6% and 19.2%.