Abstract: In order to achieve the integer multiplication operation in the RV32IM processor, The "M" standard extension of the integer multiplication of the RISC-V instruction set is implemented. For achieving the design for multiplication instructions, it uses the Booth algorithm of Base 4 and the Wallace Tree 4-2 Compressor.The design embedded in the RV32IM processor, through the simulation and SMIC 65nm high density standard cell library to show that:The multiplication circuit functions correctly and significantly improved the operation efficiency of the multiplication, the maximum operating frequency can reach 500MHz.