Abstract: As an open source processor architecture with rapid development in recent years, RISC-V has high industrial application value in the research of its verification method. In this paper, an optimization scheme of processor verification based on the genetic evolution strategy is proposed, which uses a genetic algorithm to generate instruction weight coefficients to determine the direction for the generation of test cases, and some instructions of RV32I of the RISC-V processor are simulated and verified.Compared with the scheme based on the pseudo-random strategy to generate test cases, the application of genetic evolution strategy to generate test cases can maintain a higher contribution to the function coverage.When it is about to fall into a locally optimal solution at the end of verification, it is still able to break out of the current state, allowing a further improvement of the overall functional coverage. At the same time, the verification optimization scheme realizes the automatic adjustment of the verification environment and has high scalability and maintainability.