聂廷远, 李坤龙, 高久顼. 布图规划约束对VLSI设计性能的影响[J]. 微电子学与计算机, 2016, 33(11): 104-108.
引用本文: 聂廷远, 李坤龙, 高久顼. 布图规划约束对VLSI设计性能的影响[J]. 微电子学与计算机, 2016, 33(11): 104-108.
NIE Ting-yuan, LI Kun-long, GAO Jiu-xu. The Influence on VLSI Design Performance by Constraints in Floorplanning[J]. Microelectronics & Computer, 2016, 33(11): 104-108.
Citation: NIE Ting-yuan, LI Kun-long, GAO Jiu-xu. The Influence on VLSI Design Performance by Constraints in Floorplanning[J]. Microelectronics & Computer, 2016, 33(11): 104-108.

布图规划约束对VLSI设计性能的影响

The Influence on VLSI Design Performance by Constraints in Floorplanning

  • 摘要: 布图规划处于芯片物理设计的前端, 对VLSI整体性能起着至关重要的作用.给出了平面布图规划约束的介绍, 通过在布图规划阶段进行约束嵌入的实验, 考查了约束对VLSI布图规划设计性能的影响.在IBM-HB+ Benchmark Suites上嵌入约束的实验表明, 约束设置会给VLSI布图规划带来一定的影响, 甚至会改善设计质量.

     

    Abstract: The floorplanning plays a vital role to the final VLSI performance because it is in the earlier stage of the physical design. In this paper, we introduce several kinds of constraints in floorplanning. We investigate the influence caused by constraint in floorplanning. The experimental results on IBM-HB+ Benchmark Suites show that the constraint embedding had some influence on the floorplanning design, sometimes it may improve the quality of the design.

     

/

返回文章
返回