Abstract: Metastability of digital circuits can lead to data error. Synchronous register chains are often used to reduce the probability of metastability. In order to quantify the probability of data error caused by metastable state, this paper analyzes the reason of metastable transfer in synchronous register chain according to the essence of metastable state. The precise formula of metastable stability time considering the effect of linear delay and logic gate delay is derived. A new metastable test circuit is designed to calculate the probability of occurrence of three metastable output results. Based on the mean time to failure (MTBF), the bit error rate (BER) of synchronization chain and the whole system due to metastability are calculated, and the measures to reduce the BER of the system are given.