Abstract: In order to optimize the delay and power consumption of the multiplier, a new compressor and a new compression algorithm are designed for the partial product compression part of the multiplier. Based on this, a new design of 18 bit multiplier is proposed and implemented. The new compressor reduces the delay by optimizing the lateral carry path for the characteristic that the conventional compressor has a large time lag for lateral carry. The new compression algorithm uses a binary tree structure for parallel processing, and compared with the conventional tree structure, its wiring is simple and its structure is regular.