一种多数据集混合累加电路设计
An Architecture Design for Multiple Datasets Accumulation
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摘要: 提出了一种包含输入缓存FIFO、加法器及其控制逻辑、存储单元三个部分的电流注入累加模块(Node Injected Current Accumulation, NICA), 解决了流水线阻塞大, 控制逻辑复杂、累加混合的问题, 并在此基础上采取分批处理的方式, 减少了累加的延时, 最终节省了硬件资源.在Virtex-7 690T开发板上综合布线后, 得到了较好的硬件资源消耗结果, 满足了EMTP系统的实时性仿真要求.Abstract: This paper propose anNICA(Node Injected Current Accumulation) module consists of FIFO, adder with control logic and memory. We solve the problem of large blocking, complex control logic, hybrid accumulation. On this basis, with the method of batching, we reduce the delay, finally save the hardware resources. Using a Xilinx Virtex-7 FPGA as the target device, we implement our designs and present good performance.
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