Abstract: Based on the FPGA platform, a parallel computing structure for SVM hardware implementation is proposed. The structure design of each module is accomplished by using Verilog HDL language, then simulation and experimental verification are carried out. Simulation results show that compared with Libsvm training time, the parallel architecture achieves a speed-up ratio of 3.5 times. The experimental results show that with the same parameters, the classification performance of this structure is superior to the Libsvm slightly, the classification effect is guaranteed, and the maximum clock frequency can reach 190.331 MHz, it has high computational efficiency.