郑朝霞, 资义纯, 田园, 吴浩. 高速双域乘法器设计及其应用[J]. 微电子学与计算机, 2016, 33(5): 1-5.
引用本文: 郑朝霞, 资义纯, 田园, 吴浩. 高速双域乘法器设计及其应用[J]. 微电子学与计算机, 2016, 33(5): 1-5.
ZHENG Zhao-xia, ZI Yi-chun, TIAN Yuan, WU Hao. Design and Application of High Speed Dual-Field Multiplier[J]. Microelectronics & Computer, 2016, 33(5): 1-5.
Citation: ZHENG Zhao-xia, ZI Yi-chun, TIAN Yuan, WU Hao. Design and Application of High Speed Dual-Field Multiplier[J]. Microelectronics & Computer, 2016, 33(5): 1-5.

高速双域乘法器设计及其应用

Design and Application of High Speed Dual-Field Multiplier

  • 摘要: 双域乘法器在椭圆曲线密码学中具有重要意义, 是构成双域模乘器的重要组件.考虑到双域乘法器的关键路径主要由GF (p)域决定; 因此, 在传统的基4 Booth编码乘法器的基础上进行优化设计, 改进部分积产生电路以及Wallace压缩电路, 使其能够同时支持GF (p)域和GF (2 m)域.设计的双域乘法器在FPGA实现结果表明, 双域乘法器比单独实现两个域面积减小16.9%;延时比单独的GF (p)域增加1.188 ns.将设计的双域乘法器应用到模乘器, 结果表明, 该设计完成一次256 bit的模乘操作比已有的在时间上节约了7.35%.

     

    Abstract: Dual-Field multiplier is the important component of Dual-Field Montgomery multiplier and has important meaning for elliptic curve cryptography. Considering that the critical path of Dual-Field multiplier depends on the GF(p) field, Partial product generating circuit and Wallace compressor circuit was optimized based on traditional radix-4 Booth encoder multiplier(GF(p)) to support both GF(p) and GF(2 m) field. The designed Dual-Field multiplier implemented on FPGA shows that the area is decreased by 16.9% compare to the separating implement. The delay is increased by 1.188 ns than the traditional field GF(p). The designed Dual-Field multiplier is applied to Montgomery multiplier. The time for 256 bit Montgomery multiplier of our design is reduced by 7.35% than paper proposed.

     

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