胡广垠, 王子欧, 吴升光, 王申卓. 基于高效约束解决算法的浮点数生成器设计[J]. 微电子学与计算机, 2016, 33(11): 78-82, 86.
引用本文: 胡广垠, 王子欧, 吴升光, 王申卓. 基于高效约束解决算法的浮点数生成器设计[J]. 微电子学与计算机, 2016, 33(11): 78-82, 86.
HU Guang-yin, WANG Zi-ou, WU Sheng-guang, WANG Shen-zhuo. Design of Floating Point Number Generator Based on High-Efficiency Constraint Solving Algorithm[J]. Microelectronics & Computer, 2016, 33(11): 78-82, 86.
Citation: HU Guang-yin, WANG Zi-ou, WU Sheng-guang, WANG Shen-zhuo. Design of Floating Point Number Generator Based on High-Efficiency Constraint Solving Algorithm[J]. Microelectronics & Computer, 2016, 33(11): 78-82, 86.

基于高效约束解决算法的浮点数生成器设计

Design of Floating Point Number Generator Based on High-Efficiency Constraint Solving Algorithm

  • 摘要: 为了对微处理器中浮点运算单元FPU(floating-point unit)进行高效的功能验证, 对浮点运算的边界情况进行了研究, 引入了对中间结果(intermediate result)的约束解决算法(constriant solved arithmetic).与传统的对浮点运算单元的功能验证相比, 基于该约束算法的浮点数生成器, 拓宽了浮点边界情况的可选范围, 有效提高了验证效率.实验结果表明, 集成该浮点数生成器的UVM验证平台, 能够在12小时的测试时间内, 对一个浮点运算子模块(floating-point subunit)达到超过99%的覆盖率.

     

    Abstract: In order to verify the function of the floating-point unit in the microprocessor high-efficiently, numerous corner cases of floating-point arithmetic has been studied. Several arithmetics are introduced to solve the constriants of the intermediate results. Compared with the traditional function verification of floating-point unit, the floating-point number generator based on the constraint solved algorithms has widened the scope of the optional floating-point corner cases, which effectively improves the verification efficiency.Experimental results show that the UVM verification platform which integrated the generator can test one floating-point subunit efficiently, which achieves high coverage beyond 98%, within 12 hours of testing time.

     

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