熊涛, 蒋见花. 基于UVM验证方法学的纵向可重用研究[J]. 微电子学与计算机, 2016, 33(4): 64-68.
引用本文: 熊涛, 蒋见花. 基于UVM验证方法学的纵向可重用研究[J]. 微电子学与计算机, 2016, 33(4): 64-68.
XIONG Tao, JIANG Jian-hua. Research of Vertical Reuse Based on UVM[J]. Microelectronics & Computer, 2016, 33(4): 64-68.
Citation: XIONG Tao, JIANG Jian-hua. Research of Vertical Reuse Based on UVM[J]. Microelectronics & Computer, 2016, 33(4): 64-68.

基于UVM验证方法学的纵向可重用研究

Research of Vertical Reuse Based on UVM

  • 摘要: 现在片上系统(SOC)的复杂度和集成度越来越高, 这给验证带来了巨大的挑战.传统的验证方法存在各种不足, 在效率方面已经远远达不到生产的要求.UVM是近年来兴起的一种高效的通用验证方法学, 不仅可以缩短验证周期, 而且具有很好的可重用性.UVM验证方法学的可重用主要分为横向的可重用和纵向的可重用, 主要阐述了UVM中纵向可重用的方法, 并以APB总线为例, 描述了从模块级到系统级的验证平台的搭建方法, 这种方法很好地体现了纵向重用提高验证效率的优势.

     

    Abstract: As the complexity and size of SOC(System on chip)grow, verification of design faces huge challenge. There are many defects in the traditional verification so that it can't meet the demand of manufacture in the aspect of efficiency. UVM is a universal verification methodology which springs up in recent years and has high efficiency. It can not only shorten the period of verification, but also can be reused conveniently. The reuse of UVM mainly includes Horizontal reuse and Vertical reuse. This paper focuses on the Vertical reuse and takes the APB bus as example, to expatiate how to build a verification platform from module level to system level. The methodology obviously shows that the Vertical reuse has the advantage of improving verification efficiency.

     

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