刘伟, 柴镇, 周浩杰, 吴东, 柴志雷. FPGA运行时重构的延迟隐藏机制研究与实现[J]. 微电子学与计算机, 2016, 33(8): 40-44, 49.
引用本文: 刘伟, 柴镇, 周浩杰, 吴东, 柴志雷. FPGA运行时重构的延迟隐藏机制研究与实现[J]. 微电子学与计算机, 2016, 33(8): 40-44, 49.
LIU Wei, CHAI Zhen, ZHOU Hao-jie, WU Dong, CHAI Zhi-lei. Research and Implementation of Delay Hidden Mechanism for FPGA Runtime Reconfiguration[J]. Microelectronics & Computer, 2016, 33(8): 40-44, 49.
Citation: LIU Wei, CHAI Zhen, ZHOU Hao-jie, WU Dong, CHAI Zhi-lei. Research and Implementation of Delay Hidden Mechanism for FPGA Runtime Reconfiguration[J]. Microelectronics & Computer, 2016, 33(8): 40-44, 49.

FPGA运行时重构的延迟隐藏机制研究与实现

Research and Implementation of Delay Hidden Mechanism for FPGA Runtime Reconfiguration

  • 摘要: 设计并实现了一种FPGA运行时重构的延迟隐藏机制, 通过在FPGA中进行页面管理、缓存架构设计、缓存策略研究, 在多个任务运行时调度中, 可以对用户隐藏BIT文件配置的延迟, 提高了总体运行效率.从而使FPGA具备了和GPU一样的用户模式, 为FPGA更广泛地用于计算领域提供了技术思路.

     

    Abstract: This paper designs and realizes a delay hidden mechanism for FPGA runtime reconfiguration. Through the pages management of FPGA, the cache architecture design and caching policy research, the mechanism can hid the configuration delay of BIT file, improve the overall efficiency in the multiple tasks scheduling. It gives FPGA the same user mode with GPU, provides the idea of using FPGA in computing technology more widely.

     

/

返回文章
返回