A gate-level placement and routing algorithm design for QCA circuits

Quantum-Dot Cellular Automata (QCA) is considered asa promising solution to overcome the limitations ofconventional CMOS. Recently, the development of automated design tools for QCA circuits has attracted more and more attention from researchers, where the placement and routing algorithm is a critical step. The key issue of an algorithm design is the constraints of a clock scheme and clock synchronization. Agate-level placement and routing algorithm is proposed. The path information is pre-calculated and cached within the layout region constrained by the clock scheme, and the depth-first search strategy is applied to search for the correct circuit placement routing results. The algorithm is implemented in C++ programming language, and simulation results verify the correctness of the proposed algorithm.