Background calibration and FPGA implementation of comparator offset in SHA-less pipelined ADC

In order to resolve the defect of comparator offset (including aperture error and static comparator offset) degrading the overall performance of high speed SHA-less pipelined ADC, an effective background digital calibration method is proposed. The detection of calibration is implemented by collecting the output residual voltage in digital domain, and the correction of calibration is implemented by controlling and configuring the DAC in analog domain. The calibration uses the difference of the mean values and the sum of extremums of the residueto characterize the aperture error and static comparator offset respectively, which avoids the disadvantages brought by other non-idealities in calibration, improves the ADC performance for high speed input, and improves the stability effectively.The proposed calibration method is applied in a 2.5 GS/s12bit ADC based on FPGA implementation. In this work, simulation and prototype verification are carried out to validate the practicability of the proposed method.The SNDR is improved by over 8dB@1.913GS/s based on the measurement. The calibration method decreases the difficulty of SHA-less pipelined ADC design, and relaxes the requirement of analog design, which provides reference for further high speed and low power ADC design.