Design of a new floating point multiplier based on hybrid compression structure

In order to further improve the performance of Floating-Point Multiplier and shorten the critical path delay of Floating-Point Multiplier, a hybrid compression structure based on new 4-2 compressor and 5-2 compressor is proposed. On the xc7a35tcsg324 development board of xillinx, the 32-bit Floating-Point Multiplier of IEEE754 standard is implemented based on this structure. Compared with the existing compression methods, the LUT resource and critical path delay are reduced by 45 and 0.004ns respectively. Compared with the traditional Floating-Point Multiplier, the critical path delay is reduced from 6.022ns to 4.673ns, which improves the performance of the Floating-Point Multiplier.